Memory devices find ubiquitous use in electronic devices, such as in consumer electronics. Memory devices are typically used to store executable code and data for the runtime operation of the electronic device. While better performance at lower power is a constant pursuit of newer memory devices and memory subsystems, there is typically a tradeoff between performance, power, and cost. There are many performance settings and factors that contribute to both the performance and power consumption of memory devices, and it may not be possible to provide general settings to achieve both across commodity devices (i.e., generally available, high volume memory devices used in most consumer electronics). Memory devices are tested to determine if they will perform according to design expectations to handle the stresses of runtime operation, and if they achieve acceptable performance at generic settings. Even if they achieve acceptable performance, standard settings may not provide the best performance solution for a specific system.
Communication between memory devices and other components (e.g., the memory controller, a processor) on the host platform has several performance characteristics of interest. In general, the communication with the memory device can be referred to as I/O (input/output), and is governed by standards at least for performance characteristics related to I/O power, I/O latency, and I/O frequency. The different performance characteristics can sometimes have conflicting objectives. For example, the I/O with a memory device could be performed at a higher frequency, which would typically increase the power consumption. Thus, increasing performance for one characteristic frequently has a negative impact on at least one other characteristic. Additionally, the standards or nominal values of I/O performance settings are set to values that can be achieved across different systems.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.